target-arm/translate.c@disas_thumb_insn;
target-arm/translate.c@gen_st32;
target-arm/translate.c@store_cpu_offset;
target-arm/translate.c@gen_neon_widen;
target-arm/translate.c@gen_set_condexec;
target-arm/translate.c@gen_arm_shift_reg;
target-arm/translate.c@gen_vfp_msr;
target-arm/translate.c@gen_neon_dup_low16;
target-arm/translate.c@gen_arm_shift_im;
target-arm/translate.c@disas_thumb2_insn;
target-arm/translate.c@gen_addq_lo;
target-arm/translate.c@gen_set_psr;
target-arm/translate.c@gen_addq;
target-arm/translate.c@gen_logicq_cc;
target-arm/translate.c@gen_neon_dup_high16;
target-arm/translate.c@gen_mulu_i64_i32;
target-arm/translate.c@disas_neon_ls_insn;
target-arm/translate.c@disas_dsp_insn;
target-arm/translate.c@gen_add_carry;
target-arm/translate.c@disas_arm_insn;
target-arm/translate.c@gen_intermediate_code_internal;
target-arm/translate.c@gen_thumb2_parallel_addsub;
target-arm/translate.c@neon_store_reg;
target-arm/translate.c@gen_bx_im;
target-arm/translate.c@gen_swap_half;
target-arm/translate.c@gen_ld32;
target-arm/translate.c@gen_load_exclusive;
target-arm/translate.c@gen_iwmmxt_address;
target-arm/translate.c@gen_vfp_mrs;
target-arm/translate.c@load_cpu_offset;
target-arm/translate.c@gen_op_iwmmxt_setpsr_nz;
target-arm/translate.c@gen_neon_mull;
target-arm/translate.c@gen_st8;
target-arm/translate.c@disas_cp15_insn;
target-arm/translate.c@gen_set_CF_bit31;
target-arm/translate.c@gen_arm_parallel_addsub;
target-arm/translate.c@gen_exception;
target-arm/translate.c@neon_store_scratch;
target-arm/translate.c@gen_storeq_reg;
target-arm/translate.c@gen_st16;
target-arm/translate.c@gen_addq_msw;
target-arm/translate.c@gen_test_cc;
target-arm/translate.c@gen_neon_trn_u8;
target-arm/translate.c@disas_cp_insn;
target-arm/translate.c@gen_neon_trn_u16;
target-arm/translate.c@store_reg;
target-arm/translate.c@gen_subq_msw;
target-arm/translate.c@gen_ld8u;
target-arm/translate.c@gen_add_data_offset;
target-arm/translate.c@disas_cp14_write;
target-arm/translate.c@gen_iwmmxt_shift;
target-arm/translate.c@gen_neon_dup_u8;
target-arm/translate.c@dead_tmp;
target-arm/translate.c@load_reg;
target-arm/translate.c@disas_vfp_insn;
target-arm/translate.c@gen_smul_dual;
target-arm/translate.c@gen_ld8s;
target-arm/translate.c@gen_add_datah_offset;
target-arm/translate.c@gen_muls_i64_i32;
target-arm/translate.c@gen_ld16s;
target-arm/translate.c@gen_rev16;
target-arm/translate.c@iwmmxt_store_creg;
target-arm/translate.c@gen_ld16u;
target-arm/translate.c@disas_neon_data_insn;
target-arm/translate.c@shifter_out_im;
target-arm/translate.c@gen_store_exclusive;
target-arm/translate.c@gen_adc;
target-arm/translate.c@gen_exception_return;
target-arm/translate.c@disas_iwmmxt_insn;
target-arm/translate.c@neon_load_scratch;
target-arm/translate.c@cp15_tls_load_store;
target-arm/translate.c@gen_add16;
target-arm/translate.c@gen_sub_carry;
target-arm/translate.c@iwmmxt_load_creg;
target-arm/translate.c@new_tmp;
target-arm/translate.c@gen_rfe;
target-arm/translate.c@gen_set_psr_im;
target-arm/translate.c@neon_load_reg;
